GR740 User Day on 28. November 2019 at ESTEC, Erasmus Auditorium
Welcome – Introduction to and history of the NGMP and GR740 development.
Roland Weigand
European Space Agency
After the MA31750, the first space microprocessor developed in Europe in the early 90s with MIL-STD-1750A Instruction Set Architecture (ISA), the transition to the open standard SPARC ISA was made, and several generations of SPARC microprocessors have been developed under ESA authority in the 90s and early 2000s. Today, including many FPGA implementations, several thousands of SPARC processors have been flying in space.
To prepare the transition to a multi-core, higher performance processor, the preliminary GINA (Giga Instruction New Architecture) study, using a quad-core LEON3, was completed in 2006.
The development of the GR740 was initiated in 2009 under the code name Next Generation Microprocessor (NGMP) with Cobham Gaisler, and conducted under various ESA (TRP/GSTP) contracts and own investment. Early prototypes in commercial technology and evaluation boards were made available in 2013.
The design was ported as of 2014 to the newly available C65SPACE 65 nm ASIC platform from ST Microelectronics, EM prototypes and evaluation boards have become available in Q2/2016. Thereafter, flight parts have been developed, packaged, functionally and radiation tested, and space qualification is currently in progress.
The NGMP/GR740 development was funded by various ESA programmes (TRP/GSTP/EOPP), as well as internal industry investment.
The chip development is accompanied by numerous activities to develop and improve the software ecosystem (compiler, operating system, hypervisor, timing analysis tools etc.).
Last edited Thu Dec 5 09:05:23 2019
